PIT0=0, DMACHMUX=0, FTFA=0, PDB=0, PORTM=0, LPUART=0, LPTMR=0, PORTK=0, AFE=0, CRC=0, RNGA=0, PORTL=0, PORTJ=0, PIT1=0, ADC=0
System Clock Gating Control Register 6
| FTFA | FTFA Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| DMACHMUX | DMA Channel MUX Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| RNGA | RNGA Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPUART | LPUART Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ADC | SAR ADC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PIT0 | PIT0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PIT1 | PIT1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| AFE | AFE Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CRC | Programmable CRC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PDB | PDB Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTJ | PCTLJ Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTK | PCTLK Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTL | PCTLL Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTM | PCTLM Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| LPTMR | LPTMR Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |