Regviz

Freescale Semiconductor /MKM34Z7 /SIM /SCGC6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC6

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Freescale Semiconductor/MKM34Z7/SIM/SCGC6#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)FTFA 0 (0)DMACHMUX 0 (0)RNGA 0 (0)LPUART 0 (0)ADC 0 (0)PIT0 0 (0)PIT1 0 (0)AFE 0 (0)CRC 0 (0)PDB 0 (0)PORTJ 0 (0)PORTK 0 (0)PORTL 0 (0)PORTM 0 (0)LPTMR

PORTL=0, PORTJ=0, RNGA=0, CRC=0, ADC=0, FTFA=0, PIT0=0, DMACHMUX=0, PIT1=0, LPUART=0, PORTM=0, PDB=0, LPTMR=0, AFE=0, PORTK=0

Description

System Clock Gating Control Register 6

Fields

FTFA

FTFA Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
DMACHMUX

DMA Channel MUX Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
RNGA

RNGA Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LPUART

LPUART Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
ADC

SAR ADC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PIT0

PIT0 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PIT1

PIT1 Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
AFE

AFE Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
CRC

Programmable CRC Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PDB

PDB Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTJ

PCTLJ Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTK

PCTLK Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTL

PCTLL Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
PORTM

PCTLM Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled
LPTMR

LPTMR Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

Links

()

Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data